module ALU (
    input   logic   [2:0]   ctrl,
    input   logic   [31:0]  A,
    input   logic   [31:0]  B,
    output  logic   [31:0]  F
);


// verilator lint_off WIDTH
always_comb begin
    case (ctrl)
        3'd0: F = A & B;
        3'd1: F = A | B;
        3'd2: F = A ^ B;
        3'd3: F = ~(A | B);
        3'd4: F = A + B;
        3'd5: F = A - B;
        3'd6: F = (A < B) ?'b1 :'b0;
        3'd7: F = B << A;
        default: F = 'd0;
    endcase
end
// verilator lint_on WIDTH


endmodule
